The display panel usually comprises a display region and a border region surrounding the display region. The border region may be provided with various structures, such as a driving circuit, a common electrode. The driving circuit usually comprises a plurality of thin film transistors and signal lines, and may further comprise other circuit elements, such as capacitors. At present, the border of a liquid crystal display is tended to become increasingly narrower. However, the distribution of the circuit elements and the signal lines in the border region is directly related to the size of the border region.
Reference is made to FIG. 1, which shows a schematic view of an existing layout of the wiring and the transistor in the border region. As shown FIG. 1, the border region comprises a signal line region A1, a transistor region A2, and a common electrode line region A3. Herein, the signal line region A1 may be provided with a plurality of signal lines 224, 225, and 226. The transistor region A2 may be provided with a gate electrode, a source electrode, and a drain electrode of the transistor. The common electrode line region A3 may be provided with a common electrode line 223 connected to the common electrode in parallel. FIG. 2 shows a schematic cross-sectional view of an array substrate containing the structure of the border region shown in FIG. 1. As shown in FIG. 2, the array substrate comprises a display region 2A and a non-display region 2B. The display region 2A comprises a transistor 210, a pixel electrode 24, and a common electrode 26. The non-display region 2B comprises the signal line region A1, the transistor region A2, and the common electrode line region A3. Herein, the signal line region A1 is provided with the signal lines 224, 225, and 226, which may be used as signal lines for a gate driving circuit or a source driving circuit. The signal lines may be, for example, clock signal lines used for transmitting signals for circuit elements in the gate driving circuit or the source driving circuit. The transistor region A2 is provided with a transistor 220 comprising a gate electrode 211, a source electrode 221, and a drain electrode 222. Alternatively, the transistor 220 may further comprise an amorphous silicon layer 25. The common electrode line region A3 is provided with the common electrode line 223 connected to the common electrode 26. It can be viewed from FIG. 2 that the source electrode 221 and the drain electrode 222 of the transistor 220, the common electrode line 223, and the signal lines 224, 225, and 226 are disposed on the same layer in the non-display region 2B, according to the prior design of the array substrate. Besides, the signal line region A1, the transistor region A2, and the common electrode line region A3 are arranged in parallel and do not intersect with each other.
The width of the display device border is determined by the width of the above-mentioned non-display region 2B. In order to guarantee the proper operation of the array substrate, the width of the signal line, the interval between the signal lines, and the width of the common electrode line have certain constraints. Meanwhile, in consideration of the cutting precision during the manufacturing process, it is difficult to further reduce the width of the display device border containing the non-display region 2B, and thus the design of a narrow border is difficult to achieve.